3. RISC

RISC stands for Reduced Instruction Set Computer.

The general arrangement of a RISC machine is shown below.

Now the philosophy is reversed - design a relatively simple CPU decoder with many registers at the expense of having to write more lines of code to do the same thing.

The RISC approach has some significant advantages however. For example an instruction only takes a single cycle to complete compared to the multi-cycle cisc approach.

Consider a multiply command :

CISC: MULT a,b

Whilst doing the same thing with a RISC cpu needs a number of instructions

This means more memory is needed to store the instructions, but they may actually run faster overall because each one only takes a single cycle. Furthermore, there is less movement in and out of main memory as there are more registers to hold temporary data.

Also the commands LOAD a and LOAD b are independent so there is an opportunity for parallel processing, thus improving performance

The downside is that the complier must convert a high level language instruction into many lines of machine code.